Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!unix.cis.pitt.edu!yahoo
From: yahoo@unix.cis.pitt.edu (Kenneth L Moore)
Newsgroups: sci.electronics
Subject: Re: PAL's vs gates
Message-ID: <21960@unix.cis.pitt.edu>
Date: 29 Jan 90 23:30:20 GMT
References: <358@poppy.warwick.ac.uk>
Reply-To: yahoo@unix.cis.pitt.edu (Kenneth L Moore)
Organization: Univ. of Pittsburgh, Comp & Info Services
Lines: 17

In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes:

=>     I'm thinking about building a board for my A500, however some slightly
=>involved logic is required. Is there any intrinsic benfit from using PAL's
=>rather than separate logic chips - apart from the obvious board looking
=>nicer/reduced chip count. I have no facilities for programming pals and so do
=>not want to go to the trouble if they have no advantages - other than
=>mentioned above, which I can live with.

=>Stuart Millington.

The PAL should be faster as there is no chip to chip barrier. Would speed be
important in an "A500" board? Whatever that is.


-- 
I don't yell and I don't tell and I'm grateful as hell: Benny Hill