Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!zaphod.mps.ohio-state.edu!samsung!cs.utexas.edu!asuvax!mcdphx!hrc!hw-4h625!nogeea
From: nogeea@hw-4h625.UUCP (Allen Nogee)
Newsgroups: sci.electronics
Subject: Re: PAL's vs gates
Summary: EPLDs
Message-ID: <48589642.1205f@hw-4h625.UUCP>
Date: 30 Jan 90 15:42:09 GMT
References: <358@poppy.warwick.ac.uk>
Organization: gte
Lines: 18

In article <358@poppy.warwick.ac.uk>, phupp@warwick.ac.uk (S Millington) writes:
> 
>      I'm thinking about building a board for my A500, however some slightly
> involved logic is required. Is there any intrinsic benfit from using PAL's
> rather than separate logic chips - apart from the obvious board looking
> nicer/reduced chip count. I have no facilities for programming pals and so do
> not want to go to the trouble if they have no advantages - other than
> mentioned above, which I can live with.


You might want to also consider EPLDs.  (Eraseable Programmable Logic Devices)
With ALTERA being a major vendor.  I use these many times in my designs at
work.  These are much more powerful than PALs but also more expensive.  They
can be erased and reprogrammed.  Several companies sell IBM PC card type
programmers.  

It might cost more at first to get started with EPLDs, they have much more
uses in the long run.