Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!umich!samsung!cs.utexas.edu!uunet!mcsun!ukc!warwick!phupp
From: phupp@warwick.ac.uk (S Millington)
Newsgroups: sci.electronics
Subject: Re: PAL's vs gates
Message-ID: <386@lily.warwick.ac.uk>
Date: 31 Jan 90 09:31:21 GMT
References: <358@poppy.warwick.ac.uk> <21960@unix.cis.pitt.edu>
Reply-To: phupp@warwick.ac.uk (S Millington)
Organization: Computing Services, Warwick University, UK
Lines: 22

In article <21960@unix.cis.pitt.edu> yahoo@unix.cis.pitt.edu (Kenneth L Moore) writes:
>In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes:
[deleted]
>=>Stuart Millington.
>
>The PAL should be faster as there is no chip to chip barrier. Would speed be
>important in an "A500" board? Whatever that is.
>
>--
>I don't yell and I don't tell and I'm grateful as hell: Benny Hill


   The A500 is a Comodore Amiga A500. As for speed the logic is being used to
control multi-board 68000 bus request-grant-acknowleges ( up to 5 boards) and
to prevent multiple boards responding to the same event. I'll have to have
a close look at the timing and see if I can get away with fast 74 series
chips. Thanks to all.



Stuart Millington.
phupp@poppy.