Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!mcsun!sunic!tut!ma62141
From: ma62141@etana.tut.fi (Antila Marko)
Newsgroups: sci.electronics
Subject: Re: PAL's vs gates
Message-ID: <10955@etana.tut.fi>
Date: 31 Jan 90 13:58:30 GMT
References: <442@ssc.UUCP>
Sender: News@tut.fi
Lines: 41

From article <442@ssc.UUCP>, by markz@ssc.UUCP (Mark Zenier):
> In article <1990Jan29.225838.2711@athena.mit.edu>, chuck@mitlns.mit.edu writes:
>>     I too am a budding pal user. Most of my designs require low cost and
>> low power. I note that the standard PALs are available from JDR for
>> $2.50-$5.00, which is in my range.  But these chew up 30-50ma.  Are there

> Some of the old/fast ones take up to 180 mA. gack.

>> any fully static cmos chips available? I.e. << 1ma when not switching?
>> Any that are cheap and readily available?

> Three different lines.

> GALs from Lattice. (And National ?)
> PEELS from ICT, and Gould.
> EP-3x0's from Altera and Intel

A PEEL18CV8 (Programmable, Electrically-Erasable Logic) chip from ICT
consumes 20mA + 0.7mA/MHz and maximum typical delay is 35ns. It costs
about 8FIM (less than 2US$) apiece, less in quantities. When we
ordered 50 pcs of these chips we got also some pc software for
programming these devices. 

The PEEL18CV8 - chip consists of 10 inputs and 8 outputs/inputs.    
One of the inputs can also be configured as master clock input. 
Internally it has synchronous set and asynchronous reset, and 8
macrocells.

This data is from ICT's "PEEL Software and Applications Handbook."

I'm just happy (and heavy) PEEL-user, no other associations with ICT.

> ... some references deleted ...

> markz@ssc.uucp


*   Marko  Antila  (ma62141@tut.fi)  ! Studying Wonders of    *
*  Tampere University of Technology  ! Electronics @ TTKK     *
* Signal Processing Lab, P.O.Box 527 ! ====================== *
*      SF-33101 Tampere, Finland     ! Vacuum tube rules OK   *