Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!aplcen!uunet!ingr!phil From: phil@ingr.com (Phil Johnson) Newsgroups: sci.electronics Subject: Re: PAL's vs gates Message-ID: <8590@ingr.com> Date: 1 Feb 90 14:26:51 GMT References: <358@poppy.warwick.ac.uk> Reply-To: phil@ingr.UUCP (Phil Johnson) Organization: Intergraph Corp. Huntsville, Al Lines: 31 In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes: > > I'm thinking about building a board for my A500, however some slightly >involved logic is required. Is there any intrinsic benfit from using PAL's >rather than separate logic chips - apart from the obvious board looking >nicer/reduced chip count. I have no facilities for programming pals and so do >not want to go to the trouble if they have no advantages - other than >mentioned above, which I can live with. The use of programmable logic devices (PAL, IFL, etc) can reduce the total chip count of a design, therefore reduce the cost in most cases. The cost savings is part of the design cycle, so you will need to cost the discrete versus the PLD design. The reduction factor will vary according to the circuit, but you can normally get 3 to 12 chips (7400-type) into a single PLD. Also, by reducing the chip count you can normally expect a more reliable circuit. An example would be an address decoder circuit using 4 to 6 discrete chips versus a single PLD. (QUALIFIER: Reliability is directly proportional to the care taken in the circuit design and selecting the parts.) Most local manufacturers office or distributors have the programming facilities and allow you to bring in either a fuse equation table or fuse file, buy the PLD from them and then program the device. I recommend that you look at several different types of PLDs. I use PALs, but have found the the Signetic IFLs produce a higher reduction factor for a number of designs. -- Philip E. Johnson UUCP: usenet!ingr!b3!sys_7a!phil MY words, VOICE: (205) 772-2497 MY opinion!