Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!portal!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: sci.electronics
Subject: Re: PAL's vs gates
Message-ID: <26516@cup.portal.com>
Date: 2 Feb 90 06:11:17 GMT
References: <358@poppy.warwick.ac.uk>
Organization: The Portal System (TM)
Lines: 21

For a person without a programmer, the Logic Cell Array (LCA) family from
Xilinx comes to mind.  They're more like little gate arrays than they are
like PAL's.  Their configuration bits are static RAM cells programmed using
any of a number of modes (selected by holding pins high or low).  You can
hook the LCA up to an EPROM, and let it read the bits in.  You can clock
the bits in like a shift register.  You can strobe the bits in in parallel,
like a FIFO.  You can even set up one LCA to read in its configuration in
parallel from a ROM, then daisy chain all the rest of the LCA's in the system
like a big shift register.
 
Another possibility is the ispGAL16Z8 (and that's the short form of the name,
which doesn't specify speed or package type!) which can receive its
programming serially, like a shift register.  It's made by Lattice (or will
be made by Lattice).  It uses EEPROM bits, so the serial interface is only
needed for reprogramming.  (isp stands for in-system programmable.)  It's an
architectural superset of the 16Z8, but has four more pins.  I'll bet there's
some simple way to program this thing from a regular serial port, if you just
dig out the baud rate clock.

Possible second source for these chips is AMD, who has sued all the PLD
companies, and gotten cross-licensing agreements with several of them.