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From: pkr@maddog.sgi.com (Phil Ronzone)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <3674@odin.SGI.COM>
Date: 7 Feb 90 00:39:53 GMT
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <1990Feb5.211208.15741@utzoo.uucp>
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In article <1990Feb5.211208.15741@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>No, they've figured out how to make tomorrow's CISC chips perform the
>simpler instructions in the same clock cycle that yesterday's RISC chips
>took to perform similarly simple operations.  The complicated instructions
>are still slow (and still rarely used), the RISCs still have a built-in
>lead due to shorter design times, and the CISCs still have a built-in
>handicap due to the mass of instruction/decoding/exception baggage
>dragging along behind their RISC-like cores.


Hmm, like automatic TLB loading, or that even more rarely used set known
as MUL and DIV??? :-)

------Me and my dyslexic keyboard----------------------------------------------
Phil Ronzone   Manager Secure UNIX           pkr@sgi.COM   {decwrl,sun}!sgi!pkr
Silicon Graphics, Inc.               "I never vote, it only encourages 'em ..."
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