Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: CISC Silent Spring
Message-ID: <1990Feb7.164102.22001@utzoo.uucp>
Organization: U of Toronto Zoology
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <1990Feb5.211208.15741@utzoo.uucp> <3674@odin.SGI.COM>
Date: Wed, 7 Feb 90 16:41:02 GMT

In article <3674@odin.SGI.COM> pkr@maddog.sgi.com (Phil Ronzone) writes:
>>... and the CISCs still have a built-in
>>handicap due to the mass of instruction/decoding/exception baggage
>>dragging along behind their RISC-like cores.
>
>Hmm, like automatic TLB loading, or that even more rarely used set known
>as MUL and DIV??? :-)

Automatic TLB loading is not worth the hardware needed to do it, as
Mips (among others) has clearly demonstrated.  And most RISCs do something
about multiplication and division, although sometimes the "something" is
a carefully-considered decision, based on extensive simulations, to leave
it to software.  (Of course, sometimes the same decision is made without
the careful consideration and extensive simulation... :-( )  I haven't
heard many complaints about having to live without TranslateAndTest or 
EvaluatePolynomial instructions. :-)
-- 
SVR4:  every feature you ever |     Henry Spencer at U of Toronto Zoology
wanted, and plenty you didn't.| uunet!attcan!utzoo!henry henry@zoo.toronto.edu