Path: utzoo!attcan!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <2101@crdos1.crd.ge.COM>
Date: 7 Feb 90 20:08:12 GMT
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <38415@apple.Apple.COM>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 19

In article <38415@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:

| It is still very significant that the are claiming to be faster AT THE SAME
| COLCK RATE. It also took them a few more years to build the complex chip
| that would do that- not an easy task, even with the extra time. The Moto
| folks appear to have done a very nice job on the design of this chip.

  This is very impressive. I would like to propose using MISC instead of
CISC, since the microcode which used to require many cycles per
instruction is now replaced by hard logic for virtually all of the
instructions, maybe all in the 040. I expect the 586 to have 1+
instructions per cycle average, too, indicating that traditional RISC
may have been the way to go when chips were small, and that richer
instruction sets may become possible in the next decade without giving
up any performance.

-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
            "Stupidity, like virtue, is its own reward" -me