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From: jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <19233@dartvax.Dartmouth.EDU>
Date: 8 Feb 90 06:57:40 GMT
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <38415@apple.Apple.COM> <2101@crdos1.crd.ge.COM>
Sender: news@dartvax.Dartmouth.EDU
Organization: Dartmouth College, Hanover, NH
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In article <2101@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes:
>In article <38415@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
>
>| It is still very significant that the are claiming to be faster AT THE SAME
>| COLCK RATE. It also took them a few more years to build the complex chip
>| that would do that- not an easy task, even with the extra time. The Moto
>| folks appear to have done a very nice job on the design of this chip.
>
>  This is very impressive. I would like to propose using MISC instead of
>CISC, since the microcode which used to require many cycles per
>instruction is now replaced by hard logic for virtually all of the
>instructions, maybe all in the 040. I expect the 586 to have 1+
>instructions per cycle average, too, indicating that traditional RISC
>may have been the way to go when chips were small, and that richer
>instruction sets may become possible in the next decade without giving
>up any performance.


Yes, but how much do we benefit from the richer instruction sets, even
if all the instruction are hardwired and execute at 1 cycle/instruction?
Isn't one of the RISC folks' main arguments for simple instruction sets
that current compilers don't effectively exploit the complex addressing
modes and instructions supported in CISC chips?  Perhaps someone would
like to speculate on what progess the next decade will bring in
compiler technology...

-- Jeff Kuskin, Dartmouth College

jskuskin@eleazar.dartmouth.edu