Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: New instructions for RISCs (was Re: Byte ordering)
Keywords: bitblt
Message-ID: <168@zds-ux.UUCP>
Date: 8 Feb 90 21:05:58 GMT
References: <7345@pdn.paradyne.com>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 20

In article <7345@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes:
>Of course, it would be nice if there were a single machine instruction that
>could achieve the effect of "(srcWord & mask) | (destWord & ~mask)," where
>"mask" is either a field of 1 bits followed by a field of zero bits, or else
>vice versa.

This might be a candidate instruction for future RISC designs.  Unfortunately
it has the difficulty of being a three operand instruction, so you would
have to designate a fixed register for the mask operand or it would need
a new instruction format (in conflict with an important RISC design goal).

The question is does it meet other RISC design criterion, I think it might.
Given that RISCs are very often used in workstations with bit mapped
screens, and the inner loops of various graphics functions that can use
such an instruction have very high frequencies of execution, such an
instruction is likely to be a win.  Also, three logical operations should
be pretty easy for the ALU to do fast enough for a single cycle without
stretching the cycle any.

Gerry Gleason