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From: scott@bbxsda.UUCP (Scott Amspoker)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <604@bbxsda.UUCP>
Date: 8 Feb 90 15:54:36 GMT
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <38415@apple.Apple.COM> <2101@crdos1.crd.ge.COM> <19233@dartvax.Dartmouth.EDU>
Reply-To: scott@bbxsda.UUCP (Scott Amspoker)
Organization: Basis International,  Albuquerque, NM
Lines: 22

In article <19233@dartvax.Dartmouth.EDU> jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) writes:
>Yes, but how much do we benefit from the richer instruction sets, even
>if all the instruction are hardwired and execute at 1 cycle/instruction?
>Isn't one of the RISC folks' main arguments for simple instruction sets
>that current compilers don't effectively exploit the complex addressing
>modes and instructions supported in CISC chips?  Perhaps someone would
>like to speculate on what progess the next decade will bring in
>compiler technology...

Well, it doesn't take much to find instructions on a 680x0 that are
not used by a C compiler.  However, my code tends to do a lot of
structure accesses with pointers such as "pointer->field".  The
68020 double-indirect-with-offset addressing mode is a real life
saver and I haven't seen that on the few RISC machines I've used.
Admittedly, a good optimizing compiler would not need such a
mode.

-- 
Scott Amspoker
Basis International, Albuquerque, NM
(505) 345-5232
unmvax.cs.unm.edu!bbx!bbxsda!scott