Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!mcgill-vision!bloom-beacon!mintaka!yale!think!samsung!usc!apple!portal!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <26735@cup.portal.com>
Date: 9 Feb 90 00:42:42 GMT
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP>
  <38415@apple.Apple.COM>
Organization: The Portal System (TM)
Lines: 18

>It is still very significant that the[y] (Moto about the 040)
>are claiming to be faster AT THE SAME
>COLCK RATE. It also took them a few more years to build the complex chip
>that would do that- not an easy task, even with the extra time.

Well, it's not entirely clear what clock rate means here.  It is 
interesting to note that the 040 doubles the clock internally and
uses four edges.  The "execute pipeline stage" does all of the
following *in one clock cycle*:  register read, ALU, and register
writeback.  That hardly sounds like a pipeline comparable to other
optimized pipelines.  Question:  could a 25 MHz 040 operate at
50 MHz with a better pipeline?  It seems the answer is yes.  What
does this say about RISC vs. CISC?  I don't know, and besides I
am speculating anyway.

REGARDLESS, the 040 is a really great chip and it will make some
damn nice Macintoshes.  Add a graphics accelerator (using a RISC,
let's say), and WOW!