Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!pdn!oz!alan
From: alan@oz.nm.paradyne.com (Alan Lovejoy)
Newsgroups: comp.arch
Subject: Re: New instructions for RISCs (was Re: Byte ordering)
Keywords: bitblt
Message-ID: <7366@pdn.paradyne.com>
Date: 9 Feb 90 03:19:06 GMT
References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP>
Sender: usenet@pdn.paradyne.com
Reply-To: alan@oz.paradyne.com (Alan Lovejoy)
Organization: AT&T Paradyne, Largo, Florida
Lines: 62

In article <168@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
>In article <7345@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes:
>>Of course, it would be nice if there were a single machine instruction that
>>could achieve the effect of "(srcWord & mask) | (destWord & ~mask)," where
>>"mask" is either a field of 1 bits followed by a field of zero bits, or else
>>vice versa.

>This might be a candidate instruction for future RISC designs.  Unfortunately
>it has the difficulty of being a three operand instruction, so you would
>have to designate a fixed register for the mask operand or it would need
>a new instruction format (in conflict with an important RISC design goal).

Yes, I was aware of the problem you raise.  I'm still thinking about how to
ameliorate it.  Let me broadcast some ideas on it, perhaps it will inspire
someone to generate the optimum solution.

What's wanted is an instruction, call it "splice," which does the following:

;assume a word is 32 bits
SPLICE	Rd, Rs, Rb; Rd = ((Rd >> Rb) << Rb) | ((Rs << (32 - Rb)) >> (32 - Rb))

Contents of Rd, Rs and Rb before instruction executes:
Rb = 00000000000000000000000000000111 (7 decimal)
Rs = 00000000000000000000000000000000 
Rd = 11111111111111111111111111111111

Contents of Rd, Rs and Rb after instruction executes:
Rb = 00000000000000000000000000000111 (7 decimal)
Rs = 00000000000000000000000000000000
Rd = 11111111111111111111111110000000

So SPLICE moves the rightmost Rb bits of Rs into Rd, leaving the leftmost
BitsPerWord-Rb bits of Rd unchanged.  Perhaps there should be "splice left"
and "splice right" instructions?

Perhaps more general, and hence more widely usefull would be a "bit merge"
instruction, as follows:

BMERGE Rd, Rs, Rm; Rd = (Rd & ~Rm) | (Rs & Rm)

Contents of Rd, Rs and Rm before instruction executes:
Rm = 00000000000001111111111100000000
Rs = 11000101011010000000110010110010 
Rd = 00011010111101111100000111101000

Contents of Rd, Rs and Rm after instruction executes:
Rm = 00000000000001111111111100000000
Rs = 11000101011010000000110010110010 
Rd = 00011010111100000000110011101000

For each bit of Rm which is set, BMERGE moves the corresponding bit of Rs
into Rd.  For each bit of Rm which is clear, BMERGE leaves Rd unchanged.

This uses the "destination register" as if it were the destination register
in a two-operand machine, only there are three operands.  Does this cause
undue problems for RISC?


____"Congress shall have the power to prohibit speech offensive to Congress"____
Alan Lovejoy; alan@pdn; 813-530-2211; AT&T Paradyne: 8550 Ulmerton, Largo, FL.
Disclaimer: I do not speak for AT&T Paradyne.  They do not speak for me. 
Mottos:  << Many are cold, but few are frozen. >>     << Frigido, ergo sum. >>