Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!kddlab!icot32!nttlab!nttyrl!nttmhs!yam@nttmhs.ntt.jp
From: yam@nttmhs.ntt.jp (Toshihiko YAMAKAMI)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <4684@nttmhs.ntt.JP>
Date: 8 Feb 90 21:10:43 GMT
References: <2101@crdos1.crd.ge.COM>
Sender: news@nttmhs.ntt.JP
Lines: 36

From article <2101@crdos1.crd.ge.COM>, by davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr):

>   This is very impressive. I would like to propose using MISC instead of
> CISC, since the microcode which used to require many cycles per
> instruction is now replaced by hard logic for virtually all of the
> instructions, maybe all in the 040. I expect the 586 to have 1+
> instructions per cycle average, too, indicating that traditional RISC
> may have been the way to go when chips were small, and that richer
> instruction sets may become possible in the next decade without giving
> up any performance.

It is impressive. In the next design, we have to think about
how we can fill 5,000,000 transistors or more on one chip which
LSI technology will offer us.

I agree on this point.

However, how about exploiting hidden parallelism?
As disucssed  in this group, RISC technology has exploited
hidden parallelism in high level language descriptions.
When one accesses a variable on a memory, a RISC chip loads it
into its register. Then it does some operation on it.
The value is remained on the register. One can reuse it
in another operation.
Current RISC optimizing compilers make use of it in a certain
art level.

I am very intersted in another RISC/CISC war in this decade, 1990s.

-- Toshihiko YAMAKAMI


Toshihiko YAMAKAMI	NTT Telecommunication Networks Laboratories
 Telephone:	+81-468-59-3781 	FAX:	+81-468-59-2546
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