Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!umich!samsung!zaphod.mps.ohio-state.edu!lavaca.uh.edu!uhnix1!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch Subject: Re: New instructions for RISCs (was Re: Byte ordering) Keywords: bitblt Message-ID: <79N15F5xds13@ficc.uu.net> Date: 9 Feb 90 14:58:16 GMT References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP> Reply-To: peter@ficc.uu.net (Peter da Silva) Organization: Xenix Support, FICC Lines: 16 In article <168@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes: > In article <7345@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes: > >Of course, it would be nice if there were a single machine instruction that > >could achieve the effect of "(srcWord & mask) | (destWord & ~mask)," where > >"mask" is either a field of 1 bits followed by a field of zero bits, or else > >vice versa. To really make this useful you need a "load word bit-aligned" operator, or you're still going to be dominated by masking and shifting to get the source word into memory in the first place. It'd also satisfy the people who want wimpy stuff like byte-aligned reads. > This might be a candidate instruction for future RISC designs. Unfortunately > it has the difficulty of being a three operand instruction, Why is that a difficulty? Three-operand instructions are common in RISCs. -- _--_|\ Peter da Silva. +1 713 274 5180. . / \ \_.--._/ Xenix Support -- it's not just a job, it's an adventure! v "Have you hugged your wolf today?" `-_-'