Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!oscsunb!djh
From: djh@osc.edu (David Heisterberg)
Newsgroups: comp.arch
Subject: Re: New instructions for RISCs (was Re: Byte ordering)
Keywords: bitblt
Message-ID: <139@oscsunb.osc.edu>
Date: 10 Feb 90 17:44:59 GMT
References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP> <79N15F5xds13@ficc.uu.net>
Organization: Ohio Supercomputer Center, Columbus, OH, USA
Lines: 38

In article <79N15F5xds13@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes:
> In article <168@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
> > In article <7345@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes:
> > >Of course, it would be nice if there were a single machine instruction that
> > >could achieve the effect of "(srcWord & mask) | (destWord & ~mask)," where
> > >"mask" is either a field of 1 bits followed by a field of zero bits, or else
> > >vice versa.
> 
> To really make this useful you need a "load word bit-aligned" operator, or
> you're still going to be dominated by masking and shifting to get the source
> word into memory in the first place. It'd also satisfy the people who want
> wimpy stuff like byte-aligned reads.
> 
> > This might be a candidate instruction for future RISC designs.  Unfortunately
> > it has the difficulty of being a three operand instruction,
> 
> Why is that a difficulty? Three-operand instructions are common in RISCs.
> -- 
Note that this is a three *source* operand instruction.  As I understand it,
one of the principles behind 3 operand instructions is idempotency.  CRAY
systems implement this instruction, the scalar merge, and have to sacrifice
idempotency in this case by overwriting one of the source operands.  The
usual syntax is:

	Si	Sj!Si&Sk

That is, register Si is replaced by ((Si & Sk) | (Sj & ~Sk)).  Most other
CRAY scalar instructions are of the form:

	Si	Sj op Sk

I don't understand your comment about needing a "load word bit-aligned"
operator; CRAYs certainly don't have such a thing, and are not byte adressable,
yet the scalar merge is a useful instruction.

David J. Heisterberg			djh@osc.edu
The Ohio Supercomputer Center		djh@ohstpy.binet
Columbus, Ohio				ohstpy::djh