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From: tom@.parcom.nl (Tom van Peer)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <204@parcom.parcom.nl>
Date: 11 Feb 90 22:36:24 GMT
References: <2101@crdos1.crd.ge.COM> <4684@nttmhs.ntt.JP>
Organization: Parallel Computing, Amsterdam
Lines: 19

yam@nttmhs.ntt.jp (Toshihiko YAMAKAMI) writes:

>From article <2101@crdos1.crd.ge.COM>, by davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr):

>However, how about exploiting hidden parallelism?
>As disucssed  in this group, RISC technology has exploited
>hidden parallelism in high level language descriptions.
>When one accesses a variable on a memory, a RISC chip loads it
>into its register. Then it does some operation on it.
>The value is remained on the register. One can reuse it
>in another operation.

Big fun if you want to make a multi processor set-up.

-- 
Tom van Peer.
Parallel Computing, Amsterdam.
+31-20-233274
E-mail: tom@parcom.nl