Path: utzoo!attcan!uunet!cs.utexas.edu!swrinde!ucsd!ucbvax!husc6!encore!pinocchio.encore.com
From: jdarcy@pinocchio.encore.com (Jeff d'Arcy)
Newsgroups: comp.arch
Subject: Re: '040 vs. SPARC (was: Next computer...)
Message-ID: <11117@encore.Encore.COM>
Date: 12 Feb 90 15:49:57 GMT
References: <204@parcom.parcom.nl>
Sender: news@Encore.COM
Lines: 28

Either yam@nttmhs.ntt.jp (Toshihiko YAMAKAMI)
	or davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr):
> However, how about exploiting hidden parallelism?
> As disucssed  in this group, RISC technology has exploited
> hidden parallelism in high level language descriptions.
> When one accesses a variable on a memory, a RISC chip loads it
> into its register. Then it does some operation on it.
> The value is remained on the register. One can reuse it
> in another operation.

tom@.parcom.nl (Tom van Peer):
> Big fun if you want to make a multi processor set-up.

Quite right, Tom.  In fact, it's big enough fun that doing this for any
non-local variables is probably too dangerous to try.  I don't know of any
scheme by which bus-snooper logic could tell the CPU to invalidate a value
in a register that wouldn't involve truly hideous complexity.  Fortunately,
access to shared variables is less frequent than access to locals, and in
many such cases you have to use more complex mutual-exclusion mechanisms
already.  If you have to go through all that anyway, the extra cost of not
being able to keep the value in a register is pretty negligible.

Disclaimer: I'm in OS, not compilers, so there may be issues here beyond
my ken.


Jeff d'Arcy     OS/Network Software Engineer     jdarcy@encore.com
  Encore has provided the medium, but the message remains my own