Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!brutus.cs.uiuc.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@oberon.csg.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: CISC Silent Spring Message-ID: Date: 12 Feb 90 18:50:02 GMT References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu> <3562@odin.SGI.COM> <35647@mips.mips.COM> <51951@bbn.COM> <26765@cup.portal.com> Sender: news@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 27 In-Reply-To: bcase@cup.portal.com's message of 9 Feb 90 19:34:57 GMT >>Vector machines always run faster on vector problems than non vector >>machines. Even if the cycle time is a little slower. > >I don't believe this. How about a bit of hand-waving?: If instruction dispatch is your bottleneck, vector machines are faster because they dispatch multiple operations with one instruction. Usually the operations are simple, with trivial dependencies. Really RISCy vector machines do not require hardware to resolve the possible dependencies. CISCs may dispatch multiple operations per instruction, but the dependencies are typically more complicated and the operations dispatched are less regular. Superscalar RISCs (or CISCs) dispatch multiple operations per "instruction decode cycle", but the operations dispatched are less regular and the dependencies are more general. Of course, if instruction dispatch is not your bottleneck, and you are limited by things like data memory access and dependency depth, then you use the most powerful multiple operation dispatch technique you can get away with. -- Andy Glew, aglew@uiuc.edu