Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hp-ses!hpcuhb!hpihoah!fotland
From: fotland@hpihoah.HP.COM (David Fotland)
Newsgroups: comp.arch
Subject: Re: New instructions for RISCs (was Re: Byte ordering)
Message-ID: <4420016@hpihoah.HP.COM>
Date: 13 Feb 90 00:40:07 GMT
References: <168@zds-ux.UUCP>
Organization: Hewlett Packard, Cupertino
Lines: 54


>Instead of your proposed SPLICE instruction, I'd recommend a
>BITEXT instruction which (using your notation, but where
>[x:y] means bit indexing) looks like:

>BITEXT Rd, Rs, Rdescr; Rd = Rs[Rdescr[11:6] : Rdescr[5:0]] >> Rdescr[5:0]

HP Precision Architecture has similar "extract" instructions:

VEXTRU r,len,t
(Variable extract unsigned)

The bit field in register r starting at the bit position specified by
the shift amount register, of length len (constant), is extracted and shifted
to the right of the target register.  The rest of the target is zeroed.
There is also a signed version that sign extends, and a version where the
starting bit position is in the instruction rather than the shift amount 
register.

The complementary "deposit" intructions take a right justified bit field
from the source and merges it into the target at a specified bit position.
There is also a zero and deposit that zeros the target before inserting
the bits instead of merging the bits.

The barrel shifter is in parallel with the ALU so it has little effect on
the cycle time.

>BTW, does anyone have an instruction format which uses the
>source register specifiers as an immediate small constant
>instead of a register specifier?  It seems to me, that as
>most offsets and constants are small, the use of these
>fields as direct operands, rather than having to burn a
>register and an instruction for loading a small constant,
>would be a win (even though it does start to look like
>dat ol' debbil "addressing modes" :-).

HP-PA uses register specifiers as small constants in several instructions.

There are load instructions that do base plus small immediate or base plus
index addressing.  The small immediate form has the immediate in the same place
as the index register specifier in the other instruction.

"Move immediate and branch" moves a small immediate into a register and 
branches.

"Compare immediate" and "add immediate and branch" both use 5 bit immediates in
the register field.

"Deposit immediate" deposits from a 5 bit sign extended immediate.

Some of the system control instructions use the 5 bit immediate.  The 5 bit
immediate always appears in the second register specifier field.

David Fotland