Path: utzoo!attcan!uunet!mailrus!cs.utexas.edu!halley!danh
From: danh@halley.UUCP (Dan Hendrickson)
Newsgroups: comp.arch
Subject: Re: New instructions for RISCs (was Re: Byte ordering)
Keywords: bitblt
Message-ID: <666@halley.UUCP>
Date: 13 Feb 90 14:18:22 GMT
References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP> <79N15F5xds13@ficc.uu.net>
Reply-To: danh@halley.UUCP (Dan Hendrickson)
Organization: Tandem Computers, Austin, TX
Lines: 21


In article <79N15F5xds13@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes:
>> >Of course, it would be nice if there were a single machine instruction that
>> >could achieve the effect of "(srcWord & mask) | (destWord & ~mask)," where
>> >"mask" is either a field of 1 bits followed by a field of zero bits, or else
>> >vice versa.
>
>> This might be a candidate instruction for future RISC designs.  Unfortunately
>> it has the difficulty of being a three operand instruction,
>
>Why is that a difficulty? Three-operand instructions are common in RISCs.

Yeah, but the three operands consist of two sources and one destination.  To
implement another path out of the register file to the ALU for a single inst.
would be a minimal gain.  "But then we could add this other neat xyz inst..."
Gee, isn't that why CISC's were invented?  Everyone on the architecture team
had their favorite instruction, and they wanted it included.  I would be
curious to see how often the above "bit mask" instruction would be used in
compiler-generated code.  Would the instruction be worthwhile if it slowed
the cycle time of the machine down by 10% because of the additional register
port?  Ain't nothin for free.