Path: utzoo!attcan!uunet!clyde.concordia.ca!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!halley!danh
From: danh@halley.UUCP (Dan Hendrickson)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <667@halley.UUCP>
Date: 13 Feb 90 14:29:10 GMT
References: <3300098@m.cs.uiuc.edu] <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu> <3562@odin.SGI.COM> <35647@mips.mips.COM> <51951@bbn.COM> <26765@cup.portal.com>
Reply-To: danh@halley.UUCP (Dan Hendrickson)
Organization: Tandem Computers, Austin, TX
Lines: 15

In article <26765@cup.portal.com] bcase@cup.portal.com (Brian bcase Case) writes:
]]Vector machines always run faster on vector problems than non vector
]]machines.  Even if the cycle time is a little slower.
]
]
]I don't believe this.  See the WM-machine architecture proposed by
]W. Wulf.  This is a general-purpose architecture that can achieve
]vector rates without actual vector hardware (well, the memory system
]has to be done right, but there are no vector instructions).

Has anyone ever designed the hardware for this "proposed" architecture? Or
are you comparing real iron to paper?  There are a lot of very interesting
architectures which have been proposed but never saw silicon because they
could not effectively be implemented, or if they were the penalties on the
cycle time for the hardware made them slower than the "inferior" architectures.