Path: utzoo!attcan!uunet!snorkelwacker!usc!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <52136@bbn.COM>
Date: 13 Feb 90 15:18:04 GMT
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu> <3562@odin.SGI.COM> <35647@mips.mips.COM> <51951@bbn.COM> <26765@cup.portal.com>
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Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <26765@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>Vector machines always run faster on vector problems than non vector
>>machines.  Even if the cycle time is a little slower.

>I don't believe this.  See the WM-machine architecture proposed by
>W. Wulf.  This is a general-purpose architecture that can achieve
>vector rates without actual vector hardware (well, the memory system
>has to be done right, but there are no vector instructions).

The proposed WM machine assumes a memory access unit that is
programmed to access a linear data structure with a base address, a
stride, and a length.  That's a "vector move" instruction.  The WM
combines this with a Multiflow-style RISC-VLIW instruction set and
huge register file.  I have no doubts this machine can match standard
vector machine performance; in my opinion, it also qualifies as a
vector machine, as it has all the key features.
:-) Stan