Path: utzoo!attcan!uunet!mcsun!ukc!mucs!r4!mshute
From: mshute@r4.uucp (Malcolm Shute)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <664@m1.cs.man.ac.uk>
Date: 12 Feb 90 15:47:05 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <11112@encore.Encore.COM> <753@dgis.dtic.dla.mil> <1990Feb12.025531.3609@esegue.segue.boston.ma.us>
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Reply-To: mshute@r4.UUCP (Malcolm Shute)
Organization: University of Manchester, UK
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Of course, once we are all programming our massively parallel MIMD machines,
addresses will have to include the name of the processor, as well as the
name of the data item on that processor.  These two addresses (the former
being p-bits long, and the latter d-bits) could be combined either as a
single address in (p+d)-bit address-space, or as p-bits of segment information
into 2^d sized segments

Malcolm Shute.         (The AM Mollusc:   v_@_ )        Disclaimer: all