Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hpfcso!dgr
From: dgr@hpfcso.HP.COM (Dave Roberts)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <8840009@hpfcso.HP.COM>
Date: 13 Feb 90 01:19:32 GMT
References: <9708@spool.cs.wisc.edu>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Lines: 22


If a chip production and packaging person is reading this, their head
is probably spinning.  All those signals coming out of a chip will take
a lot of chip area around the edge of a die, hence driving physical die
sizes up (and chip yields down).  They will also take a good deal of
engineering to package them.  I don't doubt that we can eventually do it,
but there are problems other than just if people need the space.
Note that this assumes that you have true 64 bit flat addresses and
64 bit data registers.

The problem isn't just that you have the extra 128 lines (64 A, 64 D) but
that you also need the extra powers and grounds to drive all of it and
not have the whole chip bounce like super ball when you put out an
address and data.

Because of this, I don't think that you'll be seeing true 64 bit address
and data for a while, at least not in the easily available range of
pricing where standard PGA microprocessors are today.

Dave Roberts
Hewlett-Packard Co.
dgr@hpfcla