Xref: utzoo comp.arch:13741 comp.compilers:785 Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!snorkelwacker!spdcc!esegue!compilers-sender From: dgb@cs.washington.edu (David Bradlee) Newsgroups: comp.arch,comp.compilers Subject: Re: Compilers and RISC (was: '040 vs. SPARC) Message-ID: <1990Feb11.040548.223@esegue.segue.boston.ma.us> Date: 11 Feb 90 04:05:48 GMT References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <1990Feb9.161153.4190@esegue.segue.boston.ma.us> Sender: compilers-sender@esegue.segue.boston.ma.us Reply-To: dgb@cs.washington.edu (David Bradlee) Organization: U of Washington, Computer Science, Seattle Lines: 43 Approved: compilers@esegue.segue.boston.ma.us In article <1990Feb9.161153.4190@esegue.segue.boston.ma.us>, Moss@cs.umass.edu writes: > My impression is that RISC chips have mostly shifted the burden but have > not really simplified the job of writing a compiler. You should also take > into account the additional complexities of dealing with instruction > scheduling and delay slot filling. I agree completely that RISCs have shifted the compiler burden, especially considering machines with multiple functional units, etc. Then, there's the Intel i860 which gives compilers lots of opportunities for work. > I do see one *possible* advantage accruing from all of this, though, which > is that instruction scheduling, delay slot filling, and register > allocation may be somewhat more machine independent in concept and more > amenable to being table driven across architectures than instruction > selection generally proves to be. This is probably true for register allocation by itself, given that RISCs typically have general purpose register sets, but it remains to be seen for instruction scheduling and for the combination of the two. Part of the problem is the specification of the information needed for scheduling (especially for something like the i860). Then there's the question of whether a particular scheduling technique will be good enough for all your desired targets. Perhaps not. The real point here is that RISCs have changed compiler needs, but there are still plenty of needs. Dave Bradlee University of Washington dgb@cs.washington.edu [Keep in mind that the IBM 801 project, the original RISC work, closely involved John Cocke, Fran Allen, and other compiler experts. The PL.8 compiler that was part of that effort is still a serious contender for world's best optimizing compiler. It has been retargeted for lots of different machines, evidently without a whole lot of work. The Berkeley project as far as I can tell involved no compiler people at all, which appears to me to be the reason that they invented register windows, being unaware of how good a job of register management a compiler can do. -John] -- Send compilers articles to compilers@esegue.segue.boston.ma.us {spdcc | ima | lotus}!esegue. Meta-mail to compilers-request@esegue. Please send responses to the author of the message, not the poster.