Xref: utzoo comp.compilers:787 comp.arch:13759
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!cica!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!usc!snorkelwacker!spdcc!esegue!compilers-sender
From: pardo@june.cs.washington.edu (David Keppel)
Newsgroups: comp.compilers,comp.arch
Subject: Re: Compilers and RISC (was: '040 vs. SPARC)
Message-ID: <1990Feb11.221418.2634@esegue.segue.boston.ma.us>
Date: 11 Feb 90 22:14:18 GMT
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <1990Feb9.161153.4190@esegue.segue.boston.ma.us> <1990Feb11.040548.223@esegue.segue.boston.ma.us>
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: pardo@june.cs.washington.edu (David Keppel)
Organization: University of Washington, Computer Science, Seattle
Lines: 31
Approved: compilers@esegue.segue.boston.ma.us

In article <1990Feb11.040548.223@esegue.segue.boston.ma.us> the
compilers moderator (John Levine) writes:
>  The Berkeley
>project as far as I can tell involved no compiler people at all, which
>appears to me to be the reason that they invented register windows, being
>unaware of how good a job of register management a compiler can do.  -John]

Somebody -- probably Wirth -- has commented that a huge portion of a
compiler's size and a huge number of its bugs come from the optimizer.
Althought I doubt the Berkeley people were making the tradeoff
consciously, I consider a *>>SIMPLE<<* hardware scheme a Good Thing if
it can replace a complicated software scheme and get nearly as good
performance as a software scheme.

Note that this is NOT the RISC argument.  This is the CISC argument,
except that I am arguing that it is OK for the performance to get
WORSE when you use hardware.  It's a provocative position and I won't
try to defend register windows.

	;-D on  ( A trend to go in circles )  Pardo
-- 
		    pardo@cs.washington.edu
    {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo
[I always thought that the Intel 432 was an extreme example of why helpful
hardware can be a bad idea.  Bug-wise, consider the size of the errata list in
any modern CISC chip, and that according to a recent comp.arch posting there
are no known bugs in the current Moto 88000 chips. -John]
-- 
Send compilers articles to compilers@esegue.segue.boston.ma.us
{spdcc | ima | lotus}!esegue.  Meta-mail to compilers-request@esegue.
Please send responses to the author of the message, not the poster.