Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!unido!tub!fauern!tumuc!guug!pcsbst! From: hgw@rht32.pcs.com (h.-g. willers) Newsgroups: comp.lang.forth Subject: Optimization Message-ID: <1990Feb9.092823.20653@pcsbst.pcs.com> Date: 9 Feb 90 09:28:23 GMT Reply-To: hgw@rht32.pcs.com (h.-g. willers) Organization: PCS Computer Systeme GmbH, D-8000 Muenchen 90 Lines: 25 Please note, that in most modern RISC-processors (such as Intels i860 or MIPSco's R2000 / R3000) there is no classical call instruction. Subroutine linkage is done with a machine register which holds the return address. So, for routines calling no further routine, there is no overhead for storing/retrieving information to/from the machine stack. Another issue, that has to be taken care of, is the 'branch delay slot' that follows a JAL (jump-and-link instruction). The branch delay slot is an instruction that is always executed after the JAL. So, we have to fill the branch delay slot with something useful (besides a NOP). That could be the first instruction of the called routine (calling effectively routine+4 on a 32-bit machine), if it is not also a branch or jump instruction. H.-G. -- H.-G. Willers PCS-Mail: hgw internal phone ( -271 ) DOMAIN: hgw@rht32.pcs.de (EUR) or hgw@rht32.pcs.com (US) BANG: ..unido!pcsbst!hgw (EUR) or ..pyramid!pcsbst!hgw (US)