Path: utzoo!attcan!uunet!pilchuck!amc-gw!sigma!flash!bill
From: bill@flash.UUCP (William Swan)
Newsgroups: comp.os.cpm
Subject: Re: 1793 Disk Contr. Info?
Message-ID: <454@flash.UUCP>
Date: 7 Feb 90 05:36:22 GMT
References: <11104@attcan.UUCP>
Reply-To: bill@flash.UUCP (William Swan)
Organization: The Keith Highlanders Pipe Band, Seattle WA
Lines: 71

In article <11104@attcan.UUCP> brian@attcan.UUCP (Brian Musker) writes:
>I can't quite make sense out of some of the data being sent to or received
>from the 1793 floppy controller.
>
>Can anyone confirm the significance of these ports?
>    RS1    RS0      PORT
>    ========================================
>     0      0       READ=STATUS, WRITE=CONTROL
>     0      1       READ/WRITE= TRACK
>     1      0       READ/WRITE= SECTOR
>     1      1       READ/WRITE= DATA

You got that correct.

>Also, does anyone know what the STATUS/CONTROL flag values might be?

The status depends upon the command given:

Bit | Type I Commands | Rd Addr | Read Sect | Rd Trk | Wr Sec | Wr Trk
7    Not Rdy            Not Rdy   etc...
6    Wr Protect (WP)                                   WP       WP
5    Head Loaded                  Rec Type            WrFault  WrFault
4    Seek Err          RecNotFNd RNF                  RNF
3    CRC err           CRC Err    CRC err             CRC err
2    Trk 00            Lost data  etc...
1    Index             Data Req   etc...
0    Busy              etc...

Control:

Type Command          7 6 5 4 3 2 1 0
I    Restore          0 0 0 0 h V r1r0
I    Seek             0 0 0 1 h V r1r0
I    Step             0 0 1 u h V r1r0
I    Step In          0 1 0 u h V r1r0
I    Step Out         0 1 1 u h V r1r0
II   Rd Sector        1 0 0 m F2E F10
II   Wr Sector        1 0 1 m F2 EF1a0
III  Rd Address       1 1 0 0 0 E 0 0
III  Rd Track         1 1 1 0 0 E 0 0
III  Wr Track         1 1 1 1 0 E 0 0
IV   Force Interrupt  1 1 0 1 I3I2I1I0

h: 1==load head @ beginning, else unload
V: 1==verify @ destination track, else don't
r1r0: step motor rate (another table = f(CLK,_DDEN, r1r0), 3ms - 416uS)
u: 1==update track register
m: 0==single record, 1==multiple records
a0:1== FB (data addr mark), else F8(deleted addr mark)
E: 1==15ms delay (2MHz), else no delay
F2: 0==compare for side 0, else compare for side 1
F1: 0==disable side select compare, else enable

IV Command:
bit 0==1 Nready to ready transition
   1     ready to nready...
   2     index pulse
   3    immediate interrupt
   all zero: terminate with no interrupt

>As far as I can tell, STATUS Bit 0 Is Controller Ready for read/write,
>and Bit 1 is some sort of Error State.

hope this helps....


-- 
Bill Swan      bill@Summation.WA.COM          Send postal address for info:
	Innocent but in prison in Washington State for 13.5 years:
	Ms. Debbie Runyan: incarcerated 01/1989, scheduled release 07/2002.
	                   In now:  1 year,   0 months,  2 weeks,  3 days.