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Path: utzoo!attcan!uunet!zephyr.ens.tek.com!uw-beaver!mit-eddie!snorkelwacker!usc!rutgers!cbmvax!grr
From: grr@cbmvax.commodore.com (George Robbins)
Newsgroups: comp.dcom.lans,comp.protocols.tcp-ip,comp.protocols.tcp-ip.ibmpc
Subject: Re: TCP Ethernet Throughput (AMD vs. Intel vs. Seeq)
Keywords: Van Jacobson, Steve Bellovin
Message-ID: <9637@cbmvax.commodore.com>
Date: 12 Feb 90 11:06:24 GMT
References: <2447@ncr-sd.SanDiego.NCR.COM> <582@berlioz.nsc.com> <29000@amdcad.AMD.COM> <29914@sparkyfs.istc.sri.com>
Reply-To: grr@cbmvax.cbm.commodore.com (George Robbins)
Organization: Commodore, West Chester, PA
Lines: 22

In article <29914@sparkyfs.istc.sri.com> rusti@milk0.itstd.sri.com.UUCP (Rusti Baker) writes:
> 
> E.G. Clark, Jacobson et al provided this insight into the 
> behavior of the LANCE in their June 1989 IEEE Comm.  article: 
> 
> "[the LANCE] locks up the memory bus during the transfer
> thus stalling the processor"

Again, this is not neccessarily an attribute of the Lance chip, but rather
how a particular interface/system implements the Lance DMA/memory interface.
A different interface might implement a (logically) dual ported buffer
memory or other scheme and thus avoid this particular constraint.

Clearly indentifying the thruput constraints for each of the major ethernet
chipsets (let along their common instantiations) would be a major task.  Chip
selection is usually done on the basis of cost, familiarity, ease of interface
and sometimes even avoidance of known problems...

-- 
George Robbins - now working for,     uucp:   {uunet|pyramid|rutgers}!cbmvax!grr
but no way officially representing:   domain: grr@cbmvax.commodore.com
Commodore, Engineering Department     phone:  215-431-9349 (only by moonlite)