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From: phil@pepsi.amd.com (Phil Ngai)
Newsgroups: comp.dcom.lans,comp.protocols.tcp-ip,comp.protocols.tcp-ip.ibmpc
Subject: Re: TCP Ethernet Throughput (AMD vs. Intel vs. Seeq)
Keywords: Van Jacobson, Steve Bellovin
Message-ID: <29138@amdcad.AMD.COM>
Date: 12 Feb 90 20:00:40 GMT
References: <2447@ncr-sd.SanDiego.NCR.COM> <582@berlioz.nsc.com> <29000@amdcad.AMD.COM> <29914@sparkyfs.istc.sri.com>
Sender: news@amdcad.AMD.COM
Reply-To: phil@pepsi.AMD.COM (Phil Ngai)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
Lines: 26

In article <29914@sparkyfs.istc.sri.com> rusti@milk0.itstd.sri.com.UUCP (Rusti Baker) writes:
|"[the LANCE] locks up the memory bus during the transfer
|thus stalling the processor"

My guess as to what was meant by this is that they are talking about the
LANCE requiring 600 ns to perform a memory cycle. That is, a zero wait
state memory cycle is 600 ns. (I don't know if you can do wait states.
This is based on my experience 6 years ago.) Although this might not
have been considered unusual when the LANCE came out in the early 80's,
10 MHz processors were only a dream at the time) it may seem slow in
an age of 25 MHz processors.

Any DMA device will lock up the memory bus, the question is how long?
The people who wrote your quote probably thought 600 ns was too long.

This is the kind of thing that a new device would probably do better.

I am not an official or unofficial spokesman for the company. This
is only my opinion.

Copyright 1990 by Phil Ngai. You may only distribute with the above
disclaimer.

--
Phil Ngai, phil@amd.com		{uunet,decwrl,ucbvax}!amdcad!phil
When guns are outlawed, only governments will have guns.