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From: marbru@auto-trol.UUCP (Martin Brunecky)
Newsgroups: comp.sys.dec
Subject: Re: Why RISC doesn't support large nuber of users?
Message-ID: <730@auto-trol.UUCP>
Date: 7 Feb 90 15:35:14 GMT
References: <25c936b0141@vms.huji.ac.il> <35387@mips.mips.COM> <673@mmlai.UUCP>
Reply-To: marbru@auto-trol.UUCP (Martin Brunecky)
Organization: Auto-trol Technology, Denver
Lines: 63

In article <673@mmlai.UUCP> burzio@mmlai.UUCP (Tony Burzio) writes:
>In article <35387@mips.mips.COM>, mark@mips.COM (Mark G. Johnson) writes:
>
>I hope the original poster was joking, but with all those gullible
>VAX architecture users out there, one can hardly take the chance :-)
>
>> The problem with Reduced Instruction Set Computers is that the
>> instruction set determines how many users a computer can handle.
>

   ... I'v been always considered a VAX bigot, but enough is enough.
   But expressing number of users machine can handle in terms of the
   instruction set size is rudiculous. May be I don't get the joke.

   There are, however, differences between RISC and CICS machines that
   may explein why 2 times faster (MIPS count) RISC box can not always
   handle 2 times more users.

   1) Code size. CICS stands for "complex" instruction set. Thus, to
      accomplish the same operation, most RISC architectures need
      more instructions. More instructions = more memory to hold'em,
      more FETCHes to get them from the memory, more I/O to page'em
      into memory.
      On busless desktop machines this ain't that important, but for
      most "midranges" use some kind of memory bus (to get to it's
      256 or more MB), and this beast is soon prone to become a bottleneck.

   2) Cache usage. The larger code size naturally requires larger
      instruction cache - otherwise all that the faster RISCy box
      can do is WAIT FASTER for the memory cycle completion.

   3) Context switch impact.
      In multiuser environment, a context switch is the name of the game.
      Context switch means that most registers must be re-loaded, that
      a significant portion of cache will become invalid ...
      Now, on machines with NO cache at all (MicroVAX is close to this
      one), the context switch will have much less impact than on SPARC
      machine with large cache and large register file to save.

   4) Overall architecture.
      Now, a computer is not only the CPU chip. It has a memory, I/O
      controllers, disks... In those areas, the progress is not measured
      by MIPS. For example, the disk I/O channel has gone from 1MB/sec
      in 1978 to 2-4MB/sec today, while the "MIPS" jumped from 1 to 20.

Overall, I don't think there is an easy answer to a quetion "how many users".
The APPLICATION is the most important component of the puzzle. And the
application may be tuned to take advantage of CICS (a VAX for example),
or tuned to take advantage of RISC. Many people are spending hours trying
to fine tune their machines (VAXen or UNIXes, does not matter), and getting
gains in 0 to 20% range. Some people are tuning applications, getting
gains in 100 - 500%+ range.

Therefore, I would allways try to look at the combination MACHINE+APPLICATION,
and forget the RISC versus CICS issue.

[ The opinions above are solely subjective, without any thoretical background
  in the field of computer architectures ].
-- 
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Martin Brunecky                   marbru@auto-trol.COM
(303) 252-2499                    {...}ncar!ico!auto-trol!marbru
Auto-trol Technology Corp. 12500 North Washington St., Denver, CO 80241-2404