Xref: utzoo comp.arch:14021 comp.lang.c:26042 comp.lang.c++:6545
Path: utzoo!attcan!uunet!mitel!sce!cognos!dgbt!gandalf!carr
From: carr@gandalf.UUCP (Dave Carr)
Newsgroups: comp.arch,comp.lang.c,comp.lang.c++
Subject: Re: RISC Machine Data Structure Word Alignment Problems?
Summary: Why not fix the RISC chips ?
Keywords: C C++ alignment
Message-ID: <2746@gandalf.UUCP>
Date: 6 Feb 90 14:09:51 GMT
References: <111@melpar.UUCP> <51385@bbn.COM> <11666@thorin.cs.unc.edu>
Lines: 19

In article <11666@thorin.cs.unc.edu>, tuck@jason.cs.unc.edu (Russ Tuck) writes:
> 
> If the compiler did what you suggest and did not align struct members,
> it would in most cases be impossible to access the data member "c" above 
> without causing the program to dump core.  This would not be a useful 
> compiler "feature" :-).  SPARC (and most other RISC archs) requires all 
> ordinary memory accesses to be aligned. 

That's *most* RISC architecture.  At least with the 80960 (I know, not a true
RISC), I have the freedom to access non word aligned data.  I would rather
have the choice than let the RISC architecture force me.

Data explosion on RISC computers is pretty bad.  We should have the choice 
between slowing the CPU down only for those accesses which are not word 
aligned.  We could pad the structures to speed it back up.
-- 
Dave Carr                |  carr@e.gandalf.ca   | If you don't know where  
Gandalf Data Limited	 |  TEL (613) 723-6500  | you are going, you will
Nepean, Ontario, Canada  |  FAX (613) 226-1717  | never get there.