Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!MATHOM.CISCO.COM!BILLW
From: BILLW@MATHOM.CISCO.COM (William "Chops" Westfield)
Newsgroups: comp.protocols.tcp-ip
Subject: Re: TCP Ethernet Throughput (AMD vs. Intel vs. Seeq)
Message-ID: <12566152530.17.BILLW@MATHOM.CISCO.COM>
Date: 14 Feb 90 01:37:29 GMT
References: <29931@sparkyfs.istc.sri.com>
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
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What happens is that the ethernet chips (both the Lance and Intel chips),
in their efforts to do fancy buffer managment, operate in a manner
similar to a processor (bus master), and have to share the bus with
the CPU chip.  To do this they implement a general purpose DMA scheme
that goes something like this:

	Ethernet: Can I have the bus?
	CPU:	OK (from this point on, the CPU can't access memory, and
		is "stalled").
	Ethernet: Lets, see, heres some address.  Now the address is valid,
		and here is some data... (and so on, hopefully for several
		words worth of data transfer).
	Ethernet: Ok, Im done.
	CPU:	Ok, I can start using the bus again...

This has the following problem:

    o	The DMA handshake takes several cycles, durring which no
	"useful" work is being done.
    o	The Lance and Intel chips both use multiplexed address/data
	pins, so that memory accesses by them take more cycles than
	they really ought to.
    o	The clock on the ethernet chip is typically 10MHz - much slower
	than most modern CPU chips.  This slows down both the memory
	accesses by the ethernet chip, and the the DMA handshake.
    o	A quick look at my lance book shows that the lance will
	take about 600 nS to read one word of memory - an eternity
	in a world of 80 nS main memory and 25 nS caches... Another
	250 nS goes by in between the time the DMA handshake finishes
	and the first DMA access starts.

So that's how ethernet controllers can "stall" a processor.  As others
have pointed out - clever hardware designs can get around this by using
dual ported memory, or other features.

Intel, AMD, and NS all have second generation chips out now.  I don't
know anything about them.  I do know that we in "higher level"
industry view any new chips with deep suspicion - early versions of
the first generation each had their share of serious bugs.  The Lance
and competitors may not be perfect, but at least they have reached the
point where they are fairly well understood.

BillW
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