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From: paulf@bodega.stanford.edu (Paul Flaherty)
Newsgroups: comp.sys.dec
Subject: Re: RISC: What did they leave out besides the instructions?
Message-ID: <1990Feb15.054555.18223@Neon.Stanford.EDU>
Date: 15 Feb 90 05:45:55 GMT
References: <60@paradigm.com>
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Reply-To: paulf@bodega.stanford.edu (Paul Flaherty)
Organization: The Three Packeteers
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In article <60@paradigm.com> gjc@paradigm.com writes:
>* RISC instruction sets are less efficient in the use of available
>  memory bandwith. 
>
>Big deal, right? "Memory is getting cheaper and cheaper"
>For most benchmarks on a single user machine the instruction-set
>cache size is sufficient so that this is not a problem. But consider
>what happens to your instruction set cache with N users.

I really don't want to get into the RISC vs CISC jihad; after all, I'm
a networks person, not an architecture hacker.

Bandwidth in the computing domain is measured in bits per second.  Memory
size (of which you speak) is measured in bits, and is not a measure of 
bandwidth.  RISC machines are less efficient in terms of both bandwidth
AND density.  Cheap memory solves the second problem, but is making the
first problem even worse, due to increases in address decoding time.
In any event, modern processors are pushing the envelope when it
comes to memory bandwidth.

>In particular a classic VAX has neither instruction cache nor stack
>cache.

Odd.  The only classic Vax that didn't have the 8KB cache was the 11/730
(and probably the 725 as well), according to my 1982 Vax Hardware Handbook.

--
-=Paul Flaherty, N9FZX/VK2WYX | "Unix could use a more user-friendly front
->paulf@shasta.Stanford.EDU   |  end.  Does anyone have a card punch handy?"