Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!snorkelwacker!mit-eddie!bu.edu!xylogics!world!paradigm!gjc
From: gjc@paradigm.com
Newsgroups: comp.sys.dec
Subject: Re: RISC: What did they leave out besides the instructions?
Message-ID: <139@paradigm.com>
Date: 19 Feb 90 17:06:02 GMT
References: <60@paradigm.com> <1990Feb15.054555.18223@Neon.Stanford.EDU> <3589@rti.UUCP>
Organization: Paradigm Associates Inc, Cambridge MA
Lines: 19

In my original "RISC" posting I talked about *specialized* cache
mechanisms vs general purpose cache mechanisms. That is why I summarized
by saying that a classic vax had NO STACK CACHE and NO INSTRUCTION cache.

Of course there is a general purpose data cache that will serve to
cache instructions or "stack" (by stack let us mean the language procedure
local variables and data structures). 

My copy of the VAX architecture manual is dated 1977, a pretty good
date for setting the classic vax architecture.

Microprocessor VAX implementations have been pretty much along classic
lines.

The failure of special purpose mechanisms for speeding up local
variable reference can be rather dramatic as a complexity
boundary is crossed. 

-gjc