Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!pt.cs.cmu.edu!b.gp.cs.cmu.edu!Ralf.Brown@B.GP.CS.CMU.EDU
From: Ralf.Brown@B.GP.CS.CMU.EDU
Newsgroups: comp.sys.ibm.pc
Subject: Re: Memory cache *and* zero wait state?
Message-ID: <25dc04c8@ralf>
Date: 16 Feb 90 12:48:56 GMT
Sender: ralf@b.gp.cs.cmu.edu
Organization: Carnegie Mellon University School of Computer Science
Lines: 22
In-Reply-To: <20154@bcsaic.UUCP>

In article <20154@bcsaic.UUCP>, nicholls@bcsaic.UUCP (Bill Nicholls) wrote:
}A local vendor is selling a 25MHz '386 system with
}
}  1 Mb ram  '0' wait state
}  32Kb cache memory
}
}What's the point of having both?
}Either I'm missing something, or the presence
}of the cache should slow the system down.

It's the cache that is making the RAM '0' wait state, unless the vendor is
using 1M of 40ns chips, which means static RAMs, which means $$$$$$$ (I
would not at all be surprised to hear that 40ns SRAMs are over a thousand
bucks a meg, particularly since there are no 1mbit SRAMs yet).

--
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"How to Prove It" by Dana Angluin              Disclaimer? I claimed something?
14. proof by importance:
    A large body of useful consequences all follow from the proposition in
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