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From: victor@hercule.cs.concordia.ca (KRAWCZUK victor)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Memory cache *and* zero wait state?
Message-ID: <1860@clyde.concordia.ca>
Date: 16 Feb 90 21:25:17 GMT
References: <25dc04c8@ralf>
Sender: usenet@clyde.concordia.ca
Reply-To: victor@hercule.CS.Concordia.CA (KRAWCZUK victor)
Organization: Concordia University, Montreal Quebec
Lines: 17

In article <25dc04c8@ralf> Ralf.Brown@B.GP.CS.CMU.EDU writes:
>
>It's the cache that is making the RAM '0' wait state, unless the vendor is
>using 1M of 40ns chips, which means static RAMs, which means $$$$$$$ (I
>would not at all be surprised to hear that 40ns SRAMs are over a thousand
>bucks a meg, particularly since there are no 1mbit SRAMs yet).
>
--

Does anyone out there think this type of chip (40 ns SRAM) will eventually
replace the ubiquitous DRAM chips in PC's?  If yes, any guesstimates??
Will mass produced DRAMS go below 70 ns???  What is the physical
limit????

       Just wondering,

             -Victor.