Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!decwrl!shelby!portia!dhinds From: dhinds@portia.Stanford.EDU (David Hinds) Newsgroups: comp.sys.ibm.pc Subject: Re: Memory cache *and* zero wait state? Message-ID: <9275@portia.Stanford.EDU> Date: 17 Feb 90 19:43:39 GMT References: <25dc04c8@ralf> <1860@clyde.concordia.ca> Sender: David Hinds Organization: Stanford University Lines: 23 In article <1860@clyde.concordia.ca>, victor@hercule.cs.concordia.ca (KRAWCZUK victor) writes: > Does anyone out there think this type of chip (40 ns SRAM) will eventually > replace the ubiquitous DRAM chips in PC's? If yes, any guesstimates?? > Will mass produced DRAMS go below 70 ns??? What is the physical > limit???? > SRAM will never replace DRAM for normal bulk main memory. SRAM requires either twice or four times as many transistors as the same amount of DRAM - I don't quite remember which. The extra circuit complexity is also a problem, I think. In any case, in terms of how difficult a chip is to make (= price, sort of), an SRAM of a given size will equal about 2 to 4 DRAMs of the same size. This seems to be confirmed by the progress and prices of SRAM chips vs. DRAMs recently. The speed improvements of DRAM's haven't fallen that far behind increases in CPU demands on memory. They are starting to now - which is why an increasingly large fraction of PC's will have static RAM caches. The speed of a chip is due to a combination of switching times and signal propagation delays. So, if you just make a chip smaller, it should get faster. I'm not sure what the physical limit is for silicon-based IC's, but it must be within an order of magnitude of present speeds (which means we are close, judging from the rate of improvement of technology). - David Hinds dhinds@popserver.stanford.edu