Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!umich!sharkey!metapyr!david
From: david@metapyr.UUCP (David Relson)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Memory cache *and* zero wait state?
Message-ID: <179@metapyr.UUCP>
Date: 19 Feb 90 18:26:20 GMT
References: <25dc04c8@ralf> <1860@clyde.concordia.ca> <9275@portia.Stanford.EDU>
Reply-To: david@metapyr.UUCP (David Relson)
Organization: Meta Systems, Ltd. -- Ann Arbor, MI
Lines: 6

DRAM's will always be cheaper than SRAM's for a given amount of storage.  DRAMs
store a value as a minute charge (a tiny capacitor).  Since capacitors lose their charge over time, DRAMs need to be refreshed periodically.  SRAMs use four 
capacitors to form a flip-flop which will remember "forever" (or until power is turned off).  This means that when the state of the art is a 4Mb DRAM, the biggest available SRAM is 1Mb (both have 4 million capacitors).

Concerning speed, SRAMs tend to be quicker.  Part of the reason is that to minimize physical size, DRAMs make double use of address pins, i.e. half the address is fed to the DRAM, then the other half, i.e. the row and column addresses.  This keeps things slower.  SRAMS tend to have sufficient pins so that this is not
necessary.