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From: sobiloff@agnes.acc.stolaf.edu (Chrome Cboy)
Newsgroups: comp.sys.mac
Subject: Re: 68040
Summary: Actually info on fast RAM
Message-ID: <11291@thor.acc.stolaf.edu>
Date: 15 Feb 90 16:55:26 GMT
References: <5221@ur-cc.UUCP> <5378@okstate.UUCP>
Sender: news@thor.acc.stolaf.edu
Reply-To: sobiloff@agnes.stolaf.edu (Chrome Cboy)
Organization: St. Olaf College, Northfield, MN
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In article <5378@okstate.UUCP> minich@a.cs.okstate.edu (MINICH ROBERT JOHN) writes:
>+ The problem with these fancy new RISC machines is that they operate at such
>  high clock rates, the design of a cache system to keep them feed is one of
>  the hardest (if not THE hardest) parts to getting the things to exploit the
>  full capabilities of the CPU. When a RISC machine doesn't get memory when it
>  wants it, it has to hold up an entire pipeline of instructions to do it, and
>  consequently clobbers effective performance.

I just read in the Wednesday edition of the Minneapolis Star Tribune that IBM
has finally started production line testing of their new 16 meg SIMMs.  The
nice thing about them is that they already are running at 50ns, and I suppose
that after IBM gets all the bugs worked out, 50ns will be the slowest of the
16 meg SIMMs.  This certainly should keep those RISC chips happy, huh?
Just FYI...
						-CCb

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