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From: cheeks@edsr.eds.com (Mark Costlow)
Newsgroups: comp.unix.wizards
Subject: Makefile Wizardry
Keywords: make makefiles help
Message-ID: <83@jupiter.UUCP>
Date: 15 Feb 90 18:41:36 GMT
Sender: usenet@jupiter.UUCP
Reply-To: cheeks@edsr.eds.com (Mark Costlow)
Followup-To: comp.unix.wizards
Organization: EDS Research, Albuquerque, NM
Lines: 80

I couldn't find a group devoted to make, so I figured wizards was the next
best thing.  I have the following situation:

I have several programs that I wish to maintain and develop source code for, 
on several different machine architectures.  I know about using link trees
(shadow directories), but I don't want to use that in this situation if I 
can avoid it.  I would like to maintain a directory structure something like
this:  (This master dir is nfs mounted by machines of different types)

/top
    /obj
        /hp300
        /sun3
        etc ...
    /src
        /prog1
        /prog2
        /prog3
        etc ...
    /bin
        hp300
        sun3
        etc ...

In my ideal configuration, I would have makefiles in each of the source 
directories which knew how to build objects and put them in the appropriate
obj and bin directories, depending on what machine type you're running the 
make on.  So, I've got makefiles that will do just about what I want, except 
for one detail:  I can't get default rules to work for targets that are of 
the form "/somedir/file.o".  I.E. when there's a dependancy of the form 
"file.o", the ".c.o" rule catches it and everything is fine, but if the 
dependency is "/top/obj/hp300/file.o", ".c.o" misses it completely.

I saw one example where somebody used a rule like this:

$(VAR1DIR)/%.o $(VAR2DIR)/%.o: %.c
	$(CC) -o $@ $<

This works just fine IF all your source files are .c files ... we're using 
at least .c, .cc, .y, and .l (many times with the same basename) files at 
any given time, so this type of dependancy doesn't work.

Here's a small sample makefile which seems to me like it should work,
but it doesn't:

-----------------------------------------------------------
all: test

.SUFFIXES:.o .c

.c.o:
        $(CC) -c -o /tmp/$*.o $*.c

test: /tmp/test.o
        $(CC) -o test /tmp/test.o

#test: test.o
#       $(CC) -o test test.o
-----------------------------------------------------------

If you use this one, you get:

Make:  Don't know how to make /tmp/test.o.  Stop.

If you uncomment the test: rule at the bottom, comment out the one
above it, and remove the /tmp/ from the .c.o rule, you have no problem.
So far I've tried this with SunOS make (3.4 and 4.0.3), HPUX make (6.2 and
7.0) and GNU Make (3.57).

I would be eternally grateful to anyone with a solution to this or a better 
idea for maintaining multiple object directories that doesn't require 
shadow directory trees or proprietary software.  If I've missed some obvious
point, please feel free to club me over the head with it.

Please email, and I'll summarize.  Thank you.

Mark

cheeks@edsr.eds.com    or     ...uunet!edsr!cheeks
cheeks@edsr.eds.com    or     ...uunet!edsr!cheeks