Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!caesar.cs.montana.edu!milton!uw-beaver!Teknowledge.COM!unix!hplabs!hp-ses!hpdmd48!sritacco
From: sritacco@hpdmd48.HP.COM (Steve Ritacco)
Newsgroups: comp.arch
Subject: Re: Error in Posting of SPEC numbers on IBM systems
Message-ID: <14900004@hpdmd48.HP.COM>
Date: 21 Feb 90 17:01:55 GMT
References: <36189@mips.mips.COM>
Organization: Hewlett Packard - Boise, ID
Lines: 39

Ok, let's talk some architecture stuff.

Why is it that the RIOS has a bigger data cache than instruction cache?
This defies conventional wisdom.  Data caches are less effective than
instruction caches and are usually made small because their hit ratio
doesn't increase with size as rapidly as instruction cache.  If I had to
guess what is going on, I would guess that access to the I-cache is
very wide, to suport super-scaler, so they crammed all they could on
the CPU chip.  This seems to be pretty effective.  IBM has shown the
super-scaler architecture works, which up to this point I wasn't convinced
of.  The benifits are tangible.  A 20MgHz CPU with 8K I-cache and 32K
D-cache SPECmarked at 22.something.  That is quite impressive.  The R3000
which to date seemed the most efficient CPU/system implementation has
been displaced for the moment.

I don't doubt that the R4000 will out-perform RIOS, there is one thing
that I wonder about though.  Will the R4000 out-perform RIOS brute force
that is high integration and very high clock speeds, or will it beat
it by providing greater architectual efficiency?  The only SPARC imple
mentations that beat mips have a major clock speed difference (not to
mention higher implemenatation cost).  One other concern is the hype
associated with super-scaler.  In the EE-Times article someone from
mips stated that the R4000 was going to be super-scaler.  That's the
first time I had heard that.  Made me wonder if it is true, or just an
attempt to ride the hype wave.  If better performance can be had with
a simpler design (non super-scaler) due to less complexity, why not tell
the world.  That is what the whole RISC-CISC thing was all about in the
first place.  The America chip set seems quite complex to me!  How does
the complexity of a design like it compare with CISC complexity?  Is it
more managable for some reason? ...

On a side note, does IBM think workstation boxes need to be ugly to
be impressive, or was their industrial design team out to lunch?


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These coments are only my own, and do not reflect te views of my
employer ...
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