Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <193@zds-ux.UUCP>
Date: 21 Feb 90 17:48:44 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <36080@mips.mips.COM> <168@csinc.UUCP>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 16

In article <168@csinc.UUCP> rpeglar@csinc.UUCP (Rob Peglar) writes:
>In summary, there are lots of codes that could be "scaled" (e.g. finer
>grids) to consume just about any D-space feasible today.  If the
>vendors want a piece of that action, >32 bits of D-space is necessary.
>Not to mention issues like memory bandwidth, I/O rates, etc.  1/2 :-)

Arn't these typically compute bound problems also?  Doesn't this mean
supercomputers?  Isn't this discussion about high volume microprocessors?

I don't remember who it was that presented the argument based on the
length of time taken to zero, let alone process 4G, but this looks like
a valid line of reasoning.  Just how many MIPS does it take before you
can process a 4G space in less than a week.  I think we're a still far
from that point.

Gerry Gleason