Path: utzoo!attcan!uunet!jarthur!elroy.jpl.nasa.gov!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <43437@ames.arc.nasa.gov>
Date: 22 Feb 90 19:52:27 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <36080@mips.mips.COM> <168@csinc.UUCP> <986@m1.cs.man.ac.uk>
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In article <986@m1.cs.man.ac.uk> mshute@r4.UUCP (Malcolm Shute) writes:
>>In article <36080@mips.mips.COM>, mash@mips.COM (John Mashey) writes:
>>> Barry has a good analysis, but I'd observe a few other things:
>addressing haven't thought through their reasoning, and realised that

>However, to change sides now, and argue the other way,
>In article <168@csinc.UUCP> rpeglar@csinc.UUCP (Rob Peglar) writes:
>>Today, I'm sure codes could use two-digit GB D-spaces (10-99 GB per
>>file) if they had it.  [...]
>physics will *allow* them to use it.  "Barry's Good Analysis",
>alluded to above, is a convincing one: how can we expect to see
>machines with 64bit adrspc until we have machines that can do useful
>things with it in small finite time?

>still be: "Not until instruction speeds are of the order of 4.0e9
>times faster than they are at present (i.e. to cover 2^64 locations
>in about the time that current processors take to cover 2^32 locations)",
>or "Not until we can get 4.0e9 times as many processors sharing the
>job of massaging all of those locations".

I don't follow this.  A Cray Y-MP memory subsystem already currently has 
40 GBytes/sec of memory bandwidth, and has the processors to chew up most of 
that bandwidth.  If you follow the rule of thumb that the processor should be
able to read/write/zero or whatever the memory in 1-10 seconds, you have 
already reached 100 GBytes.  Today.  With next generation systems
expected to have bandwidth requirements 16 times those of today, you should
be able to address Terabytes of data.  With 16 Mbit DRAMs coming out, you
can expect physical memories to reach 64 GBytes before too long.  

These numbers imply, to me, that next generation architectures need *at least* 
40 bit addressing.  It doesn't make sense to design your system with odd sized
addresses that are just barely big enough- surely we can learn something from
the history of computing.  Using the next sized power of two and keeping
address size consonant with one of the supported integer sizes is, IMHO, the
only sensible thing to do.  

Now, if you add to that the requirement for sparse address spaces, 
due to memory mapped files, distributed applications, global addressing,
and object/capability programming, and 64 bits is actually quite reasonable
*anyway*. 

Now, you may be asking, what do systems with 64 Gbytes of memory have to
do with micros, which, in the same time frame, will have maybe 256 MBytes
of memory?  Answer: If you want your KM to be used in multiple processor
systems with 32-? processors, you will easily exceed the capability of 32 bit
addressing before long.  I note that a number of *Big Iron* folks are already
designing with multiple micros.  I am certain that a system with clean
flexible 64 bit linear addressing will have a significant leg up on the 
competition when it comes to being chosen for next generation parallel 
micro-based systems.

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117