Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!pdn!oz!alan
From: alan@oz.nm.paradyne.com (Alan Lovejoy)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Message-ID: <7454@pdn.paradyne.com>
Date: 22 Feb 90 18:52:58 GMT
References: <8064@pt.cs.cmu.edu>
Sender: usenet@pdn.paradyne.com
Reply-To: alan@oz.paradyne.com (Alan Lovejoy)
Organization: AT&T Paradyne, Largo, Florida
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In article <8064@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
>
>The machine certainly has nice floating point performance for the
>price.  But I'm a little disturbed that the non-floating performance
>is so similar, per clock, to that of the conventional RISCs.  The
>chip set fills 13 square centimeters of silicon, and contains an
>order of magnitude more logic than (say) an R3000/3010 pair. It's
>superscalar, and the R3000 isn't.  So why isn't it faster per clock?
>There are two possibilities:
>
>- the tricks aren't a very good idea and didn't buy much. When
>  the competition uses all these tricks, too, it won't be
>  much of an improvement. (Naaah.)
>- when the competition uses all those tricks, too, then the 6000
>  will be revealed as deficient in some way. (But what way?)

You forgot at least one possibility, which an IBM spokesman claims just
happens to be the real reason:  the compilers have not yet been updated
to take any real advantage of the integer instruction paralellism provided
by the CPU.  Of course, some of the paralellism (5 instructions/cycle max)
is only available when FP instructions are to be executed, but the same is
true for most other "superscalars" and/or "near superscalars" which are
currently available.  Expect integer benchmark performance to much more
closely resemble the claimed "MIPS" ratings when the new compilers become
available.


____"Congress shall have the power to prohibit speech offensive to Congress"____
Alan Lovejoy; alan@pdn; 813-530-2211; AT&T Paradyne: 8550 Ulmerton, Largo, FL.
Disclaimer: I do not speak for AT&T Paradyne.  They do not speak for me. 
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