Path: utzoo!dciem!nrcaer!sce!greg
From: greg@sce.carleton.ca (Greg Franks)
Newsgroups: comp.arch
Subject: Re: 68040
Keywords: need data
Message-ID: <786@sce.carleton.ca>
Date: 22 Feb 90 15:08:32 GMT
References: <851@trane.UUCP> <7793@quick.COM> <9746@cbmvax.commodore.com>
Reply-To: greg@sce.UUCP (Greg Franks)
Organization: Systems Eng., Carleton Univ., Ottawa, Canada
Lines: 28

In article <9746@cbmvax.commodore.com> daveh@cbmvax.cbm.commodore.com (Dave Haynie) writes:
>The other real interesting thing is that some of the CISCish stuff, like
>address register increment/decrement or offset are handled at their own
>pipeline stages, so many of the non-simple instructions/addressing modes
>still execute in a single effective cycle.  I'm certain more of the
>really weird addressing modes must be handled in several cycles, though
>most compilers don't use these anyway.

The latest issue of IEEE micro is a summary of the hot-chips
symposium.  (Overall, its a very good issue).  The one thing that
struck me as interesting with regard to the new 68040 is that the
"optimized effective address" modes are almost the same as those
supported by the PDP-11.  

The article also states that the fancy addressing modes are twice as
fast on the 040 as they are on the 030 and 020.  However, since I
don't have the data books, I can't say how one complex address mode
instruction stacks up against 'n' optimized address mode instructions.

Finally, from my days of kernel writing for imbedded real-time
systems, I can state that I didn't find the "quadruple indexed through
pc on full moon" type address modes very necessary at all.

-- 
Greg Franks   (613) 788-5726     Carleton University,             
uunet!mitel!sce!greg (uucp)  	 Ottawa, Ontario, Canada  K1S 5B6.
greg@sce.carleton.ca (bitnet)	 (we're on the internet too. (finally))
Overwhelm them with the small bugs so that they don't see the big ones.