Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!rice!husc6!encore!pinocchio!peralta
From: peralta@pinocchio.Encore.COM (Rick Peralta)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <11227@encore.Encore.COM>
Date: 23 Feb 90 17:08:20 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <36080@mips.mips.COM> <168@csinc.UUCP> <193@zds-ux.UUCP>
Sender: news@Encore.COM
Reply-To: peralta@pinocchio.UUCP (Rick Peralta)
Organization: Encore Computer Corp, Marlboro, MA
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In article <193@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
>... how many MIPS does it take before you can process a 4G space...
> I think we're a still far from that point.

I suspect that these things are closer than you think.
Current designs are using multiple external busses to
hook together many CPU clusters.  There are plenty of
100Mip single bus machines and 1000Mips is just around
the corner.  So the horse power argument is rather weak.


 - Rick