Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!mips!winchester!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Message-ID: <36440@mips.mips.COM>
Date: 25 Feb 90 03:33:44 GMT
References: <9376@portia.Stanford.EDU> <192@zds-ux.UUCP> <1990Feb22.175120.12835@utzoo.uucp>
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Reply-To: mash@mips.COM (John Mashey)
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In article <1990Feb22.175120.12835@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:

>Um, I haven't followed the details of the new IBM stuff, but my impression
>is that most of the "super-scalar" parallelism being touted is just
>parallelism between integer and floating-point operations, which both
>MIPS and SPARC have had from the beginning...

Actually, this is not right.  Even with multiple function units,
and even with whatever degree of parallelism there is, none of
the {MIPS, SPARC, 88K, HP PA} set issues more than one instruction/cycle.
The IBM certainly can issue more, as does the Intel i960, and they
are superscalars.  The HP Apollo DN10000 and Intel i860 are more
properly called short-VLIWs (in my opinion), since they are restricted
to instruction pairs of 1-integer+1 FP, in a definite order.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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